1. Field
Exemplary embodiments relate to a nonvolatile memory device in which a channel of a memory cell transistor is formed vertically, a fabrication method thereof, and a memory system comprising the same. According to embodiments, when at least two NAND strings are repeatedly made by alternately stacking an insulating layer and a conductive gate layer, a bulk layer made of a conductive semiconductor material is formed between the NAND strings so that it can be used for an erase operation, and vertical layers in the NAND strings are connected to each other in a self-aligned manner. In addition, a fabrication method for this structure is also disclosed. Thus, an erase operation is performed by the bulk layer, and the interference between the bulk layer and the channel layer is minimized.
2. Description of the Related Art
As semiconductor technology has rapidly developed for several decades, the degree of integration of semiconductor memories has greatly increased. Among these memories, non-volatile semiconductor memories have made a market comparable to DRAMs due to the recent popularization of mobile devices. Particularly, among non-volatile memories, NAND flash memories are prevalent. It was difficult to improve the degree of integration of NAND flash memories, because cells that store binary information are adjacent to each other and spread horizontally. In the year 2010, a semiconductor device having a line width of 20 nm (nano-meter) was also developed. However, because the size of the device is decreased due to an increase in the degree of integration, the physical and electrical properties of the device may be deteriorated.
Flash memories typically have a structure in which a floating gate and a control gate are stacked. The flash memories are programmed by injecting electric charges into the floating gate and erased by causing the injected electric charges to escape. However, in recently developed technologies, flash memories are arranged on a semiconductor substrate vertically rather than horizontally in order to overcome the limitation on the density of integration.
In the year 2007, Toshiba Corporation (Japan) presented a flash memory including a vertical channel and a composite insulating layer of SONOS (Silicon-Oxide-Nitride-Oxide-Substrate) as a charge trap layer instead of a double-gate structure, as disclosed in an article entitled “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory” (hereinafter referred to as ‘BiCS technology’). See H. Tanaka et al., 2007 Symposium on VLSI Technology, sec 2-2, pages 14-15, which is incorporated by reference in its entirety herein for all purposes. At the 2009 Symposium on VLSI Technology (R. Katsumata et al., sec. 7-1, pages 136-137), Toshiba Corporation (Japan) presented at an article entitled “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices” (hereinafter referred to as ‘P-BiCS technology’) which is also incorporated by reference in its entirety herein for all purposes. Meanwhile, Samsung presented a flash memory having a vertical channel, in an article entitled “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory” (hereinafter referred to as ‘TCAT technology’), presented at the 2009 Symposium on VLSI Technology. (J. Jang et al., sec. 10A-4, pages 192-193). These articles are herewith incorporated by reference in their entireties herein.
However, in these technologies, as a number of vertically stacked NAND strings increases, various problems arise. For example, the BiCS technology or the P-BiCS technology employs a GIDL (Gate Induced Drain Leakage) in a lower select transistor connected to the NAND string on the semiconductor substrate during an erase operation, and in this case, erase efficiency decreases as a number of memory cells connected to the NAND string increases. Particularly, this issue becomes more prevalent in the memory cells which are located farther from the select transistor and also acts as a factor of limiting vertical stacking.
Another issue that may be associated with the TCAT technology is that an erase voltage should be applied to the substrate so that the erase voltage influences all the memory cells of the NAND string in order to perform an erase operation. In this case, an erase bias is applied through the channel region of each transistor, and thus a voltage difference is produced between the channel layer of the memory cell adjacent to the substrate and the channel layer of the memory cell located farthest from the substrate. This is because of resistivity of the channel region. For this reason, there are problems in that erase efficiency changes depending on a position of the memory cell and in that a number of memory cells which can be stacked is also limited. These problems become more severe as a number of stacked memory cells in the NAND string increases, and reduce cost competitiveness of a vertical channel-type nonvolatile memory product.